In many integrated circuits, and in particular in pixels, insulating walls are arranged between semiconductor regions to insulate them from one another. The case where the insulating walls are made of an insulated conductor, that is, where they are formed in a trench having its walls and its bottom coated with an insulating material, and being filled with a conductive material, is here more particularly considered.
FIGS. 1A, 1B, and 1C illustrate an example of a pixel 1 comprising an insulating wall made of an insulated conductor, FIG. 1A being a top view of the pixel and FIGS. 1B and 1C being cross-section views of the pixel along respective planes BB and CC of FIG. 1A. This example corresponds to an embodiment of a pixel described in U.S. application patent Ser. No. 15/136,569 filed Apr. 22, 2016 (corresponding to French Application for patent No. 15/60422 filed Oct. 30, 2015) incorporated by reference.
Pixel 1 is a pixel of an image sensor adapted to a so-called global shutter control mode, and comprises a photosensitive area, a charge storage area, or memory area, and a read area coupled to a read circuit. In a global shutter control mode, the photogenerated charges accumulated during an integration phase in the photosensitive area of each sensor pixel are simultaneously transferred into the corresponding memory area and a complete image is then stored in all the memory areas. The stored image can then be read, during the next integration phase, by transferring the charges stored in the memory areas to the corresponding read areas.
Pixel 1 is formed inside and on top of a lightly-doped P-type semiconductor substrate 3 (P−). The photosensitive area of pixel 1 comprises an N-type doped well 5 of doping level N1. At the upper surface of the substrate, well 5 is coated with a heavily-doped P-type thin layer 7 (P+). Well 5 thus forms with substrate 3 the junction of a vertically pinned photodiode, or photosite, PD. The memory area of pixel 1 comprises an N-type doped well 9 of doping level N2, well 9 being coated with P+-type thin layer 7. Well 9 thus forms with substrate 3 the junction of a vertically pinned photodiode SD. The dimensions and doping levels N1 and N2 of wells 5 and 9 are selected so that the storage capacity of diode SD is greater than or equal to that of photodiode PD.
The memory area is adjacent to an edge of the photosensitive area (at the bottom of FIG. 1A) and extends lengthwise in a direction parallel to this edge. The memory area is laterally delimited by two separate portions, or insulated vertical electrodes, 11 and 13 of an insulating wall made of a conductive material 15 coated with a layer of an insulating material 17. The insulating wall penetrates into the substrate down to a depth greater than or equal to that of well 9. Electrode 11 is arranged between the photosensitive area and the memory area, and fully delimits a first large side of the memory area. Electrode 13 comprises a portion 13A, parallel to electrode 11, fully delimiting the second large side of the memory area. At a first end of the memory area, electrode 13 further comprises an extension 13B extending from portion 13A to the photosensitive area to be opposite a first end of electrode 11 (on the left-hand side of FIG. 1A). The end of electrode 11 and the opposite portion of extension 13B define an opening 19 between the photosensitive area and the memory area, having well 5 of the photosensitive area extending therethrough all the way to well 9 of the memory area.
The rear area of pixel 1 comprises a semiconductor region 21 more heavily N-type doped (N+) than wells 5 and 9. Region 21 extends in substrate 3 from the upper surface thereof, down to a depth smaller than that of well 9. Region 21 is arranged at the second end of the memory area (on the right-hand side of FIG. 1A), opposite well 9 in line with the memory area. A portion 23 of the substrate separates well 9 from region 21. An insulated horizontal gate, or control gate, is arranged on top of and in contact with portion 23 of the substrate. This gate forms the gate of a MOS transistor 25 having its channel-forming region corresponding to portion 23 of substrate 3, and having its source and drain regions corresponding to well 9 and to region 21. Thus, the memory area extends from the photo-sensitive area to transistor 25.
The insulating wall further comprises an insulated portion or vertical electrode 27, separate from electrodes 11 and 13, and an insulated portion of vertical electrode 29, separate from electrodes 11, 13, and 27. Electrode 27 delimits most of the sides of the photosensitive area which are not bordered with the memory area. Electrode or counter-electrode 29 extends parallel to electrode 11, from an edge of the photosensitive area, beyond the second end of electrode 11 (on the right-hand side of FIG. 1A), to stop before the first end of electrode 11 (on the left-hand side of FIG. 1A). Electrode 29 partially delimits the photosensitive area on the side of the memory area.
To form electrodes 11, 13, 27, and 29, trenches vertically penetrating into substrate 3 from the upper surface thereof are etched, according to a pattern corresponding to the desired electrode shape. The lateral walls and the bottom of the trenches are coated with insulating material 17, after which the trenches are filled with conductive material 15.
Metallizations (not shown) electrically connect conductor 15 of electrodes 11 and 13 to a node CTRL1, conductor 15 of electrodes 27 and 29 to a node VPol, the gate of transistor 25 to a node CTRL2, and the upper surface of region 21 to a node SN of the pixel read circuit (not shown). The control potentials applied to nodes CTRL1 and CTRL2 of the pixel are provided by a pixel control circuit which may be common to a plurality of pixels of the sensor.
Pixel 1 is intended to receive an illumination on the upper surface or front surface side of substrate 3 and comprises a screen opaque to light (not shown) located on its upper surface side and masking the entire surface of the pixel except its photosensitive area.
The operation of pixel 1 will now be described.
In integration phase, substrate 3 and nodes VPol and CTRL1 are at a same reference voltage. This potential may be the ground potential, or may be negative with respect to ground, for example, in the order of −1 V. Such an electrode biasing causes an accumulation of holes along the walls of these electrodes, particularly in opening 19. The dimensions of opening 19, of layer 7, and of wells 5 and 9, as well as the doping levels of substrate 3, of layer 7, and of wells 5 and 9 are selected so that, in the absence of illumination and of photogenerated charges, wells 5 and 9 are fully depleted, in particular at the level of opening 19 where the depletion potential of well 5 is lower than the depletion potential of the rest of well 5. A potential well then forms in well 5 and a potential well forms in well 9. The potential levels of these wells depend on the doping levels and on the bias potentials of the electrodes and of the substrate. When pixel 1 is illuminated, electron/hole pairs are photogenerated in photodiode PD, and the photogenerated electrons are attracted and trapped in well 5, which then forms a charge accumulation area. At the level of opening 19, well 5 remains fully depleted, which blocks electron exchanges between well 5 and well 9.
In a phase of transfer of the electrons accumulated in well 5 of photodiode PD to well 9 of the memory area, node CTRL1 is set to a sufficiently high voltage, for example, in the range from 2 to 4 V, to set the potential of well 5 at the level of opening 19 to a potential higher than the maximum potential of the potential well in photodiode PD during the integration phase, and to set the maximum potential of the potential well in well 9 to a potential higher than that in well 5 at the level of opening 19. As a result, all the photogenerated electrons contained in well 5 to well 9, via opening 19 are transferred. During the transfer phase, node VPol and substrate 3 remain at the same reference potential as during the integration phase.
To read the electrons stored in the memory area, transistor 25 is set to a conductive state, which causes the transfer of electrons from well 9 to region 21 coupled to the pixel read circuit. The rest of the time, transistor 25 is in a non-conductive state, which prevents the passing of electrons from the memory area to region 21.
A disadvantage of pixel 1 is that region 21 coupled to node SN and portion 23 of substrate 3 are not laterally delimited by an insulating structure. As a result, charges may be lost during a charge transfer from the memory area to region 21. Further, charges photogenerated and accumulated in the photosensitive area may reach region 21 without having been previously transferred into the memory area. Counter-electrode 29 enables to limit such direct charge exchanges between the photosensitive area and the read area, but this causes a decrease in the photosensitive area of the pixel.
It would thus be desirable to have an insulating wall which enables to delimit semiconductor regions of a pixel and which overcomes at least some of the disadvantages of existing insulating walls.